Evan is a SystemC Source-based design environment that
provides required tools for simulation and verification
of SystemC models.
Evan’s debugging tools enables the users to make design
and verification go on much easier and faster.
V2SC is a first-in-class technology for high speed
compilation of Verilog IP modules into SystemC ones.
V2SC makes it possible to re-use pre-designed Verilog IP
cores in a new platform in which simulation is faster and
free. V2SC offers performance in simulation time and cuts
down prices.
