V2SC is a translation tool from Verilog IEEE 1364-2001 to SystemC IEEE 1666-2005.
V2SC fills in the gap between Verilog and SystemC environments.
V2SC enables SystemC users to integrate Verilog cores into their designs.
V2SC also enables IP providers to port their designs into SystemC as another option for IP core customers.
System designers can simulate huge Verilog designs (especially above RT level) much faster by using V2SC.
V2SC lets individuals simulate and debug their Verilog modules free of cost.
V2SC supports almost all Verilog constructs except for some rarely used constructs such as Charge Strength, Drive Strength, Verilog Switch Level, Procedural Continues Assignment, Specify Block and also Verilog 2001 generate statement. Of course this is not a V2SC shortcoming. These constructs are not supported in SystemC.
Download V2SC whitepaper
V2SC features:
.png) Supports Verilog HDL 2001 IEEE standard.
Translates Verilog HDL modules into SystemC 2.1 library.
Covers a large subset of Verilog language.
Coverts Verilog test-benches precisely into SystemC ones.
Designed on top of an advanced Object-Oriented Compiler technology.
Easy to change and extend due to internal object-oriented design and architecture.
Innovative solutions to convert many hard-to-translate Verilog constructs, including casex, gate-level models, waits, events, etc.
Equipped with smart algorithm which recognizes where to use two-value and where four-value logic.
Keeps design hierarchy untouched during conversion.
Available on Linux and Windows platforms.
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